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january 2007 hys72d64301[g/h]br?[5/6]?b hys72d128xxx[g/h]br?[5/6/7]?b hys72d256220[g/h]br?[5/6/7]?b hys72d256320[g/h]br?[5/6/7]?b 184 - pin registered doub le-data-rate sdram module ddr sdram rohs compliant products internet data sheet rev. 1.42
we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com internet data sheet hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module qag_techdoc_rev400 / 3.2 qag / 2006-07-21 2 03292006-7cza-ys85 hys72d64301[g/h]br?[5/6]?b, hys72d128xxx[g/h] br?[5/6/7]?b, hys72d256220[g/h]br?[5/6/7]?b, hys72d256320[g/h]br?[5/6/7]?b revision history: 2007-01, rev. 1.42 all qimonda update all adapted internet edition previous revision: 2006-03, rev. 1.41 67 editorial change previous revision: 2004-05, rev. 1.4
internet data sheet rev. 1.42, 2007-01 3 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 1overview 1.1 features ? 184-pin registered 8-byte dual-in-line ddr sdram modu le for ?1u? pc, workstation and server main memory applications ? one rank 128m 72 and 64m 72 organization, and two ranks 256m 72 organization ? standard double-data-rate synchronous dra ms (ddr sdram) with a single + 2.5 v ( 0.2 v) power supply and +2.6 v ( 0.1 v) power supply for ddr400 ? built with ddr sdrams in p-tfbga-60 package ? programmable cas latency, burst length , and wrap sequence (sequential & interleave) ? auto refresh (cbr) and self refresh ? all inputs and outputs sstl_2 compatible ? ras-lockout supported t rap = t rcd ? re-drive for all input signals using register and pll devices. ? serial presence detect with e 2 prom ? low profile modules form factor: 133.35 mm 28.58 mm (1.1?) 4.00 mm and 133.35 mm 30.48 mm (1.2?) 4.00 mm ? standard reference card layout raw card ?a?, ?b?, ?c?, ?d?. ? gold plated contacts table 1 performance part number speed code ?5 ?6 ?7 unit speed grade component ddr400b ddr333b ddr266a ? module pc3200?3033 pc2700?2533 pc2100?2033 ? max. clock frequency @cl3 f ck3 200 166 ? mhz @cl2.5 f ck2.5 166 166 143 mhz @cl2 f ck2 133 133 133 mhz
internet data sheet rev. 1.42, 2007-01 4 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 1.2 description the hys72d[64/128/256]xxx[g/h] br?[5/6/7]?b are low profile versions of the standard register ed dimm modules with 1.1? inch (28.58) and 1.2? inch (30,40 mm) height for 1u server applications. the low prof ile dimm versions are available as 64m 72(512 mb), 128m 72 (1 gb) and 256m 72 (2 gb). the memory array is designed with double data rate sync hronous drams for ecc applications. all control and address signals are re-driven on the dimm using register devices and a p ll for the clock distribution. this reduces capacitive loading to the system bus, but adds one cycle to the sdram timing. a variety of de coupli ng capacitors are mounted on the pc board. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. table 2 ordering information for lead - containing products product type 1) 1) all product types end with a place code designating the silicon-die revision. reference inform ation available on request. example: hys72d128300gbr-5-b, indicating rev.b die are used for sdram components. compliance code 2) 2) the compliance code is printed on the module labels and describes the speed sort (for example ?pc2100r?), the latencies (for example ?20330? means cas latency of 2.0 clocks, row-column-delay (rcd) latency of 3 clocks and row pre- charge latency of 3 clocks), je dec spd code definition version 0, and the raw card used for this module. description sdram technology pc3200 (cl=3) hys72d64301gbr?5?b pc2700r?30331?a0 one rank 512 mbyte reg. ecc dimm 512 mbit ( 8) hys72d128300gbr?5?b pc3200r?30331?c0 one rank 1 gbyte reg. ecc dimm 512 mbit ( 4) hys72d128321gbr?5?b pc3200r?30331?b0 two ranks 1 gbyte reg. ecc dimm 512 mbit ( 8) hys72d256220gbr?5?b pc3200r?30331?d0 two ranks 2 gbyte reg. ecc dimm 512 mbit ( 4) pc2700 (cl=2.5) hys72d64301gbr?6?b pc2700r?25330?a0 one rank 512 mbyte reg. ecc dimm 512 mbit ( 4) hys72d128300gbr?6?b pc2700r?25330?c0 one rank 1 gbyte reg. ecc dimm 512 mbit ( 4) hys72d128321gbr?6?b pc2700r?25330?b0 two ranks 1 gbyte reg. ecc dimm 512 mbit ( 8) hys72d256320gbr?6?b pc2700r?25330?d0 two ranks 2 gbyte reg. ecc dimm 512 mbit ( 4) hys72d256220gbr?6?b pc2700r?25330?d0 two ranks 2 gbyte reg. ecc dimm 512 mbit ( 4) pc2100 (cl=2) hys72d128300gbr?7?b pc2100r?20330?c0 one rank 1 gbyte reg. ecc dimm 512 mbit ( 4) hys72d128321gbr?7?b pc2100r?20330?b0 two ranks1 gbyte reg. ecc dimm 512 mbit ( 8) hys72d256220gbr?7?b pc2100r?20330?d0 two ranks 2 gbyte reg. ecc dimm 512 mbit ( 4) hys72d256320gbr?7?b pc2100r?20330?d0 two ranks 2 gbyte reg. ecc dimm 512 mbit ( 4)
internet data sheet rev. 1.42, 2007-01 5 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module table 3 ordering information for lead - free (rohs complaint) products product type 1)2) 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. 2) all product types end with a place code designating the silicon-die revision. re ference information available on request. example: hys72d128300gbr-5-b, indicating rev.b die are used for sdram components. compliance code 3) 3) the compliance code is printed on the m odule labels and describes the speed sort (for example ?pc2100r?), the latencies (for example ?20330? means cas latency of 2.0 clocks, ro w-column-delay (rcd) latency of 3 clocks and row pre-charge latency of 3 clocks), je dec spd code definition version 0, and t he raw card used for this module. description sdram technology pc3200 (cl=3) hys72d64301hbr?5?b pc3200r?30331?a0 one rank 512 mbyte reg. ecc dimm 512 mbit ( 8) hys72d128300hbr?5?b pc3200r?30331?c0 one rank 1 gbyte reg. ecc dimm 512 mbit ( 4) hys72d128321hbr?5?b pc3200r?30331?b0 two ranks 1 gbyte reg. ecc dimm 512 mbit ( 8) hys72d256220hbr?5?b pc3200r?30331?d0 two ranks 2 gbyte reg. ecc dimm 512 mbit ( 4) hys72d256320hbr?5?b pc3200r?30331?f0 two ranks 2 gbyte reg. ecc dimm 512 mbit ( 4) pc2700 (cl=2.5) hys72d64301hbr?6?b pc2700r?25330?a0 one rank 512 mbyte reg. ecc dimm 512 mbit ( 8) hys72d128300hbr?6?b pc2700r?25330?c0 one rank 1 gbyte reg. ecc dimm 512 mbit ( 4) hys72d128321hbr?6?b pc2700r?25330?b0 two ranks 1 gbyte reg. ecc dimm 512 mbit ( 8) hys72d256220hbr?6?b pc2700r?25330?d0 two ranks 2 gbyte reg. ecc dimm 512 mbit ( 4) hys72d256320hbr?6?b pc2700r?25330?f0 two ranks 2 gbyte reg. ecc dimm 512 mbit ( 4) pc2100 (cl=2) hys72d128300hbr?7?b pc2100r?20330?c0 one rank 1 gbyte reg. ecc dimm 512 mbit ( 4) hys72d128321hbr?7?b pc2100r?20330?b0 two ranks 1 gbyte reg. ecc dimm 512 mbit ( 8) hys72d256220hbr?7?b pc2100r?20330?d0 two ranks 2 gbyte reg. ecc dimm 512 mbit ( 4) hys72d256320hbr?7?b pc2100r?20330?f0 two ranks 2 gbyte reg. ecc dimm 512 mbit ( 4)
internet data sheet rev. 1.42, 2007-01 6 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 2 pin configuration the pin configuration of t he registered ddr sdram dimm is listed by function in table 4 (184 pins). the abbreviations used in columns pin and buffer type are explained in table 5 and table 6 respectively. the pin numbering is depicted in figure 1 . table 4 pin configuration of rdimm pin# name pin type buffer type function clock signals 137 ck0 i sstl clock signal 138 ck0 i sstl complement clock 21 cke0 i sstl clock enable rank 0 111 cke1 i sstl clock enable rank 1 note: 2-rank module nc nc sstl note: 1-rank module control signals 157 s0 i sstl chip select of rank 0 158 s1 i sstl chip select of rank 1 note: 2-ranks module nc nc ? note: 1-rank module 154 ras i sstl row address strobe 65 cas i sstl column address strobe 63 we i sstl write enable 10 reset ilv- cmos register reset address signals 59 ba0 i sstl bank address bus 1:0 52 ba1 i sstl 48 a0 i sstl address bus 11:0 43 a1 i sstl 41 a2 i sstl 130 a3 i sstl 37 a4 i sstl 32 a5 i sstl
internet data sheet rev. 1.42, 2007-01 7 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 125 a6 i sstl address bus 11:0 29 a7 i sstl 122 a8 i sstl 27 a9 i sstl 141 a10 i sstl ap i sstl 118 a11 i sstl 115 a12 i sstl address signal 12 note: module based on 256 mbit or larger dies nc nc ? note: 128 mbit based module 167 a13 i sstl address signal 13 note: 1 gbit based module nc nc ? note: module based on 512 mbit or smaller dies data signals 2 dq0 i/o sstl data bus 63:0 4 dq1 i/o sstl 6 dq2 i/o sstl 8 dq3 i/o sstl 94 dq4 i/o sstl 95 dq5 i/o sstl 98 dq6 i/o sstl 99 dq7 i/o sstl 12 dq8 i/o sstl 13 dq9 i/o sstl 19 dq10 i/o sstl 20 dq11 i/o sstl 105 dq12 i/o sstl 106 dq13 i/o sstl 109 dq14 i/o sstl 110 dq15 i/o sstl 23 dq16 i/o sstl 24 dq17 i/o sstl 28 dq18 i/o sstl 31 dq19 i/o sstl pin# name pin type buffer type function
internet data sheet rev. 1.42, 2007-01 8 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 114 dq20 i/o sstl data bus 63:0 117 dq21 i/o sstl 121 dq22 i/o sstl 123 dq23 i/o sstl 33 dq24 i/o sstl 35 dq25 i/o sstl 39 dq26 i/o sstl 40 dq27 i/o sstl 126 dq28 i/o sstl 127 dq29 i/o sstl 131 dq30 i/o sstl 133 dq31 i/o sstl 53 dq32 i/o sstl 55 dq33 i/o sstl 57 dq34 i/o sstl 60 dq35 i/o sstl 146 dq36 i/o sstl 147 dq37 i/o sstl 150 dq38 i/o sstl 151 dq39 i/o sstl 61 dq40 i/o sstl 64 dq41 i/o sstl 68 dq42 i/o sstl 69 dq43 i/o sstl 153 dq44 i/o sstl 155 dq45 i/o sstl 161 dq46 i/o sstl 162 dq47 i/o sstl 72 dq48 i/o sstl 73 dq49 i/o sstl 79 dq50 i/o sstl 80 dq51 i/o sstl 165 dq52 i/o sstl 166 dq53 i/o sstl 170 dq54 i/o sstl 171 dq55 i/o sstl 83 dq56 i/o sstl 84 dq57 i/o sstl 87 dq58 i/o sstl 88 dq59 i/o sstl pin# name pin type buffer type function
internet data sheet rev. 1.42, 2007-01 9 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 174 dq60 i/o sstl data bus 63:0 175 dq61 i/o sstl 178 dq62 i/o sstl 179 dq63 i/o sstl 44 cb0 i/o sstl check bits 7:0 45 cb1 i/o sstl 49 cb2 i/o sstl 51 cb3 i/o sstl 134 cb4 i/o sstl 135 cb5 i/o sstl 142 cb6 i/o sstl 144 cb7 i/o sstl 5 dqs0 i/o sstl data strobes 8:0 14 dqs1 i/o sstl 25 dqs2 i/o sstl 36 dqs3 i/o sstl 56 dqs4 i/o sstl 67 dqs5 i/o sstl 78 dqs6 i/o sstl data strobes 8:0 86 dqs7 i/o sstl 47 dqs8 i/o sstl 97 dm0 i sstl data mask 0 note: 8 based module dqs9 i/o sstl data strobe 9 note: 4 based module 107 dm1 i sstl data mask 1 note: 8 based module dqs10 i/o sstl data strobe 10 note: 4 based module 119 dm2 i sstl data mask 2 note: 8 based module dqs11 i/o sstl data strobe 11 note: 4 based module 129 dm3 i sstl data mask 3 note: 8 based module dqs12 i/o sstl data strobe 12 note: 4 based module 149 dm4 i sstl data mask 4 note: 8 based module dqs13 i/o sstl data strobe 13 note: 4 based module pin# name pin type buffer type function
internet data sheet rev. 1.42, 2007-01 10 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 159 dm5 i sstl data mask 5 note: 8 based module dqs14 i/o sstl data strobe 14 note: 4 based module 169 dm6 i sstl data mask 6 note: 8 based module dqs15 i/o sstl data strobe 15 note: 4 based module 177 dm7 i sstl data mask 7 note: 8 based module dqs16 i/o sstl data strobe 16 note: 4 based module 140 dm8 i sstl data mask 8 note: 8 based module dqs17 i/o sstl data strobe 17 note: 4 based module eeprom 92 scl i cmos serial bus clock 91 sda i/o od serial bus data 181 sa0 i cmos slave address select bus 2:0 182 sa1 i cmos 183 sa2 i cmos power supplies 1 v ref ai ? i/o reference voltage 184 v ddspd pwr ? eeprom power supply 15, 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 v ddq pwr ? i/o driver power supply 7, 38, 46, 70, 85, 108, 120, 148, 168 v dd pwr ? power supply 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 v ss gnd ? ground plane pin# name pin type buffer type function
internet data sheet rev. 1.42, 2007-01 11 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module table 5 abbrevations for pin type table 6 abbrevations for buffer type table 7 address format other pins 82 v ddid ood v dd identification 9, 16, 17, 71, 75, 76, 90, 101, 102, 103, 113, 163, 173 nc nc ? not connected abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nu not usable (jedec standard) nc not connected (jedec standard) abbreviation description sstl serial stub terminalted logic (sstl2) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-or. density organization memory ranks sdrams # of sdrams # of row/bank/ column bits refresh period interval 512 mb 64m 72 1 64m 8 8 13/2/11 8k 64 ms 7.8 s 1gb 128m 72 1 128m 4 18 13/2/12 8k 64 ms 7.8 s 1gb 128m 72 2 64m 8 18 13/2/11 8k 64 ms 7.8 s 2gb 256m 72 2 128m 4 36 13/2/12 8k 64 ms 7.8 s pin# name pin type buffer type function
internet data sheet rev. 1.42, 2007-01 12 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module figure 1 pin configuration 184 pins, reg 033' %$&.6,'( )52176,'( 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 9 5() '46 1& '4 1& '4 '4 '4 '4 '4 5(6(7 '4 '46 1& '4 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq '4 '4 $ '46 '4 &% $ %$ 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq &.( '4 '46 $ $ '4 '4 '4 $ '4 $ $ &% '46 &% &% 9 66 9 66 9 '' 9 66 9 ''4 9 ''4 9 66 9 66 9 '' 9 ''4 9 66 9 ''4 9 66 9 '' 9 66 9 '' 9 66 9 ''4 9 66 9 ''4 9 66 9 '' 9 66 9 '',' '4 '4 '4 %$ '4 :( &$6 '46 '4 1& '4 1& '4 '4 '4 6'$ '46 '4 '4 '4 '4 1& '46 '4 '4 '46 '4 1& 6&/ 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq '4 '4'46 '4 1& 1& '4 '0'46 '4 &.(1& 1& $1& '4 '0'46 '4 '4 $ '4 '0'46 '4 '4 &% &. $$3 '4 '4 1& '4 '4 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq '4 $ $ '4 $ &% &. '0'46 &% &% 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq '4 '0'46 '4 '4 '4 6 '0'46 '4 1& '4 $1& '0'46 '4 1& '4 '0'46 '4 6$ 6$ 9 ''4 9 ''4 9 ''4 9 '' 9 '' 9 66 9 66 9 66 9 66 9 ''4 9 66 9 66 9 ''4 9 ''4 9 '' 9 ''4 9 66 9 ''4 9 ''4 9 66 9 ''4 9 66 9 '' 9 66 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq '4 '4 5$6 61& '4 '4 '4 '4 '4 6$ 9 ''63' 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq
internet data sheet rev. 1.42, 2007-01 13 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 3 electrical characteristics 3.1 operating conditions table 8 absolute maximum ratings attention: permanent damage to the device may occur if ?absolute maximum ratings? are exceeded. this is a stress rating only, and functional operation should be rest ricted to recommended operation conditions. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause ir reversible damage to the integrated circuit. parameter symbol values unit note/ test condition min. typ. max. voltage on i/o pins relative to v ss v in , v out ?0.5 ? v ddq + 0.5 v ? voltage on inputs relative to v ss v in ?1 ? +3.6 v ? voltage on v dd supply relative to v ss v dd ?1 ? +3.6 v ? voltage on v ddq supply relative to v ss v ddq ?1 ? +3.6 v ? operating temperature (ambient) t a 0?+70 c? storage temperature (plastic) t stg ?55 ? +150 c? power dissipation (per sdram component) p d ?1? w? short circuit output current i out ?50? ma?
internet data sheet rev. 1.42, 2007-01 14 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module table 9 electrical characteristics and dc operating conditions parameter symbol values unit note/test condition 1) 1) 0 c t a 70 c; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v; min. typ. max. device supply voltage v dd 2.3 2.5 2.7 v f ck 166 mhz device supply voltage v dd 2.5 2.6 2.7 v f ck > 166 mhz 2) 2) ddr400 conditions apply for all clock frequencies above 166 mhz output supply voltage v ddq 2.3 2.5 2.7 v f ck 166 mhz 3) 3) under all conditions, v ddq must be less than or equal to v dd . output supply voltage v ddq 2.5 2.6 2.7 v f ck >166mhz 2)3) supply voltage, i/o supply voltage v ss , v ssq 0?0v? input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 4) 4) peak to peak ac noise on v ref may not exceed 2 % v ref.dc . v ref is also expected to track noise variations in v ddq . i/o termination voltage (system) v tt v ref ? 0.04 ? v ref + 0.04 v 5) 5) v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . input high (logic1) voltage v ih(dc) v ref + 0.15 ? v ddq + 0.3 v 6) 6) inputs are not recognized as valid until v ref stabilizes. input low (logic0) voltage v il(dc) ? 0.3 ? v ref ? 0.15 v 6) input voltage level, ck and ck inputs v in(dc) ? 0.3 ? v ddq + 0.3 v 6) input differential voltage, ck and ck inputs v id(dc) 0.36 ? v ddq + 0.6 v 6)7) 7) v id is the magnitude of the difference between the input level on ck and the input level on ck . vi-matching pull-up current to pull-down current v i ratio 0.71 ? 1.4 ? 8) 8) the ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1. 0 v. for a given output, it represents the maximum difference b etween pull-up and pull-down drivers due to process variation. input leakage current i i ?2 ? 2 a any input 0 v v in v dd ; all other pins not under test = 0 v 9) 9) values are shown per pin. output leakage current i oz ?5 ? 5 a dqs are disabled; 0 v v out v ddq 9) output high current, normal strength driver i oh ? ? ?16.2 ma v out = 1.95 v output low current, normal strength driver i ol 16.2 ? ? ma v out = 0.35 v
internet data sheet rev. 1.42, 2007-01 15 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module table 10 i dd conditions parameter symbol operating current 0 one bank; active/ precharge; dq, dm, and dq s inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. i dd0 operating current 1 one bank; active/read/precharge; burst length = 4; see co mponent data sheet. i dd1 precharge power-down standby current all banks idle; power-down mode; cke v il,max i dd2p precharge floating standby current cs v ih,,min , all banks idle; cke v ih,min ; address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs and dm. i dd2f precharge quiet standby current cs v ihmin , all banks idle; cke v ih,min ; v in = v ref for dq, dqs and dm; address and other control inputs stable at v ih,min or v il,max . i dd2q active power-down standby current one bank active; power-down mode; cke v ilmax ; v in = v ref for dq, dqs and dm. i dd3p active standby current one bank active; cs v ih,min ; cke v ih,min ; t rc = t ras,max ; dq, dm and dqs inputs changi ng twice per clock cycle; address and control inputs changing once per clock cycle. i dd3n operating current read one bank active; burst length = 2 ; reads; continuous burst; address and control inputs changing once per clock cycle; 50 % of data outputs changing on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b; i out =0ma i dd4r operating current write one bank active; burst length = 2 ; writes; continuous burst; address and control inputs changing once per clock cycle; 50 % of data outputs changing on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b i dd4w auto-refresh current t rc = t rfcmin , burst refresh i dd5 self-refresh current cke 0.2 v; external clock on i dd6 operating current 7 four bank interleaving with burst length = 4; see component data sheet. i dd7
internet data sheet rev. 1.42, 2007-01 16 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module table 11 i dd specification for hys72d[64/128/256]xxx[g/h]br?5?b product type hys72d64301gbr?5?b hys72d64301hbr?5?b hys72d128300gbr?5?b hys72d128300hbr?5?b hys72d128321gbr?5?b hys72d128321hbr?5?b hys72d256220gbr?5?b hys72d256220hbr?5?b hys72d256320hbr?5?b unit note/ test conditions 1) 2) 1) test condition for maximum values: v dd =2.7v, t a =10c 2) module i dd is calculated on the basis of component i dd and includes register and pll currents organization 512 mb 1 gb 1 gb 2 gb 72 72 72 72 1 rank 1 rank 2 ranks 2 ranks ?5 ?5 ?5 ?5 symbol typ. max. typ. max. typ. max. typ. max. i dd0 1230 1460 2250 2660 1880 2180 3550 4110 ma 3) 3) the module i dd values are calculated from the component i dd data sheet values are: n * i dd [component] for single bank modules (n : number of components per module bank) n * i dd [component] + n * i dd3n [component] for two bank modules (n: number of components per module bank) i dd1 1450 1690 2560 2980 2100 2410 3860 4430 ma 3)4) 4) dq i/o ( i ddq ) currents are not included into calculations: module i dd values will be measured di fferently depending on load conditions i dd2p 410 430 690 770 690 770 1320 1440 ma 5) 5) the module i dd values are calculated from the component i dd decathlete values are: n * i dd [component] for single bank modules (n : number of components per module bank) 2 * n * i dd [component] for single two bank modules (n : number of components per module bank) i dd2f 880 990 1450 1620 1450 1620 2590 2870 ma 5) i dd2q 530 630 1000 1160 1000 1160 1940 2230 ma 5) i dd3p 460 540 870 980 870 980 1690 1870 ma 5) i dd3n 960 1090 1610 1820 1610 1820 2910 3260 ma 5) i dd4r 1400 1600 2470 2800 2050 2320 3770 4250 ma 3)4) i dd4w 1450 1650 2560 2890 2100 2370 3860 4340 ma 3) i dd5 2210 2620 4360 5120 2870 3340 5660 6570 ma 3) i dd6 360 390 660 740 660 740 1310 1430 ma 5) i dd7 2700 3190 5620 6580 3630 4210 6920 8030 ma 3)4)
internet data sheet rev. 1.42, 2007-01 17 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module table 12 i dd specification for hys72d[64/128/256]xxx[g/h]br?6?b product type hys72d64301gbr?6?b hys72d64301hbr?6?b hys72d128300gbr?6?b hys72d128300hbr?6?b hys72d128321gbr?6?b hys72d128321hbr?6?b hys72d256220gbr?6?b hys72d256320gbr?6?b hys72d256220hbr?6?b hys72d256320hbr?6?b unit note/ test conditions 1) 2) 1) test condition for maximum values: v dd =2.7v, t a =10c 2) module i dd is calculated on the basis of component i dd and includes register and pll currents organization 512 mb 1 gb 1 gb 2 gb 72 72 72 72 1 rank 1 rank 2 ranks 2 ranks ?6 ?6 ?6 ?6 symbol typ. max. typ. max. typ. max. typ. max. i dd0 1130 1320 2060 2380 1700 1940 3190 3620 ma 3) 3) the module i dd values are calculated from the component i dd decathlete values are: n * i dd [component] for single bank modules (n : number of components per module bank) n * i dd [component] + n * i dd3n [component] for two bank modules (n: number of components per module bank) i dd1 1340 1540 2360 2690 1910 2160 3490 3930 ma 3)4) 4) dq i/o ( i ddq ) currents are not included into calculations: module i dd values will be measured di fferently depending on load conditions i dd2p 380 400 610 690 610 690 1140 1260 ma 5) 5) the module i dd values are calculated from the component i dd decathlete values are: n * i dd [component] for single bank modules (n : number of components per module bank) 2 * n * i dd [component] for single two bank modules (n : number of components per module bank) i dd2f 780 880 1250 1400 1250 1400 2200 2440 ma 5) i dd2q 480 580 890 1050 890 1050 1690 1980 ma 5) i dd3p 430 500 780 890 780 890 1480 1660 ma 5) i dd3n 870 980 1430 1600 1430 1600 2560 2840 ma 5) i dd4r 1270 1450 2210 2510 1840 2070 3340 3750 ma 3)4) i dd4w 1310 1500 2290 2600 1870 2110 3420 3840 ma 3) i dd5 2010 2360 3920 4590 2570 2970 5050 5820 ma 3) i dd6 350 390 600 680 600 680 1150 1270 ma 5) i dd7 2440 2880 5040 5910 3250 3770 6170 7150 ma 3)4)
internet data sheet rev. 1.42, 2007-01 18 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module table 13 i dd specification for hys72d[128/256]xxx[g/h]br?7?b product type hys72d128300gbr?7?b hys72d128300hbr?7?b hys72d128321gbr?7?b hys72d128321hbr?7?b hys72d256220gbr?7?b hys72d256320gbr?7?b hys72d256220hbr?7?b hys72d256320hbr?7?b unit note/ test conditions 1) 2) 1) test condition for maximum values: v dd =2.7v, t a =10c 2) module i dd is calculated on the basis of component i dd and includes register an pll organization 1 gb 1 gb 2 gb 72 72 72 1 rank 2 ranks 2 ranks ?7 ?7 ?7 symbol typ. max. typ. max. typ. max. i dd0 1780 2060 1460 1670 2700 3090 ma 3) 3) the module i dd values are calculated from the component i dd decathlete values are: n * i dd [component] for single bank modules (n : number of components per module bank) n * i dd [component] + n * i dd3n [component] for two bank modules (n: number of components per module bank) i dd1 2070 2390 1650 1900 2990 3420 ma 3)4) 4) dq i/o ( i ddq ) currents are not included into calculations: module i dd values will be measured di fferently depending on load conditions i dd2p 530 610 530 610 960 1080 ma 5) 5) the module i dd values are calculated from the component i dd decathlete values are: n * i dd [component] for single bank modules (n : number of components per module bank) 2 * n * i dd [component] for single two bank modules (n : number of components per module bank) i dd2f 1050 1180 1050 1180 1810 2010 ma 5) i dd2q 770 910 770 910 1440 1690 ma 5) i dd3p 660 770 660 770 1230 1400 ma 5) i dd3n 1210 1380 1210 1380 2140 2410 ma 5) i dd4r 1920 2170 1580 1790 2840 3200 ma 3)4) i dd4w 1990 2260 1620 1830 2920 3290 ma 3) i dd5 3570 4230 2300 2700 4490 5260 ma 3) i dd6 540 620 540 620 990 1110 ma 5) i dd7 4390 5140 2810 3270 5310 6170 ma 3)4)
internet data sheet rev. 1.42, 2007-01 19 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module table 14 ac timing - absolute specifications for pc3200 and pc2700 parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max. dq output access time from ck/ck t ac ?0.5 +0.5 ?0.7 +0.7 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 2)3)4)5) clock cycle time t ck 5 8 6 12 ns cl = 3.0 2)3)4)5) 6 12 6 12 ns cl = 2.5 2)3)4)5) 7.5 12 7.5 12 ns cl = 2.0 2)3)4)5) ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 2)3)4)5) auto precharge write recovery + precharge time t dal ( t wr / t ck )+( t rp / t ck ) t ck 2)3)4)5)6) dq and dm input hold time t dh 0.4 ? 0.45 ? ns 2)3)4)5) dq and dm input pulse width (each input) t dipw 1.75 ? 1.75 ? ns 2)3)4)5)6) dqs output access time from ck/ck t dqsck ?0.6 +0.6 ?0.6 +0.6 ns 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ? +0.40 ? +0.40 ns tfbga 2)3)4)5) write command to 1 st dqs latching transition t dqss 0.72 1.25 0.75 1.25 t ck 2)3)4)5) dq and dm input setup time t ds 0.4 ? 0.45 ? ns 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck 2)3)4)5) dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? t ck 2)3)4)5) clock half period t hp min. ( t cl , t ch )? min. ( t cl , t ch )? ns 2)3)4)5) data-out high-impedance time from ck/ck t hz ? +0.7 ? +0.7 ns 2)3)4)5)7) address and control input hold time t ih 0.6 ? 0.75 ? ns fast slew rate 3)4)5)6)8) 0.7 ? 0.8 ? ns slow slew rate 3)4)5)6)8) control and addr. input pulse width (each input) t ipw 2.2 ? 2.2 ? ns 2)3)4)5)9) address and control input setup time t is 0.6 ? 0.75 ? ns fast slew rate 3)4)5)6)8) 0.7 ? 0.8 ? ns slow slew rate 3)4)5)6)8)
internet data sheet rev. 1.42, 2007-01 20 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module data-out low-impedance time from ck/ck t lz ?0.7 +0.7 ?0.7 +0.7 ns 2)3)4)5)7) mode register set command cycle time t mrd 2?2? t ck 2)3)4)5) dq/dqs output hold time from dqs t qh t hp ? t qhs ? t hp ? t qhs ?ns 2)3)4)5) data hold skew factor t qhs ? +0.50 ? +0.50 ns tfbga 2)3)4)5) active to autoprecharge delay t rap t rcd ? t rcd ?ns 2)3)4)5) active to precharge command t ras 40 70e+3 42 70e+3 ns 2)3)4)5) active to active/auto-refresh command period t rc 55 ? 60 ? ns 2)3)4)5) active to read or write delay t rcd 15 ? 18 ? ns 2)3)4)5) average periodic refresh interval t refi ? 7.8 ? 7.8 s 2)3)4)5)10) auto-refresh to active/auto- refresh command period t rfc 65 ? 72 ? ns 2)3)4)5) precharge command period t rp 15 ? 18 ? ns 2)3)4)5) read preamble t rpre 0.9 1.1 0.9 1.1 t ck 2)3)4)5) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5) active bank a to active bank b command t rrd 10 ? 12 ? ns 2)3)4)5) write preamble t wpre 0.25 ? 0.25 ? t ck 2)3)4)5) write preamble setup time t wpres 0?0?ns 2)3)4)5)11) write postamble t wpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5)12) write recovery time t wr 15 ? 15 ? ns 2)3)4)5) internal write to read command delay t wtr 2?1? t ck 2)3)4)5) exit self-refresh to non-read command t xsnr 75 ? 75 ? ns 2)3)4)5) exit self-refresh to read command t xsrd 200 ? 200 ? t ck 2)3)4)5) 1) 0 c t a 70 c ; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v (ddr333); v ddq = 2.6 v 0.1 v, v dd = +2.6 v 0.1 v (ddr400) 2) input slew rate 1 v/ns for ddr400, ddr333 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input refe rence level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 6) for each of the terms, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. 7) t hzhz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 8) fast slew rate 1.0 v/ns , slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ns, measured between v ih(ac) and v il(ac) . 9) these parameters guarantee device timing, but th ey are not necessarily tested on each device. 10) a maximum of eight autorefresh commands can be posted to any given ddr sdram device. parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max.
internet data sheet rev. 1.42, 2007-01 21 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module table 15 ac timing - absolute spec ifications for pc2100 11) the specific requirement is that dqs be valid (high,low, or some point on a valid transition) on or before this ck edge. a v alid transition is defined as monotonic and meeting the input slew rate specificationsof the device. w hen no writes were previously in progress on the bus, dqs will be transitioni ng from hi-z to logic low. if a previous write wa s in progress, dqs could be high, low at this time , depending on t dqss . 12) the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. parameter symbol ?7 unit note/test condition 1) ddr266a min. max. dq output access time from ck/ck t ac ?0.75 +0.75 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 t ck 2)3)4)5) clock cycle time t ck 712?cl = 3 2)3)4)5) 7.5 12 ns cl = 2.5 2)3)4)5) 7.5 12 ns cl = 2.0 2)3)4)5) ck low-level width t cl 0.45 0.55 t ck 2)3)4)5) auto precharge write recovery + precharge time t dal ( t wr / t ck )+( t rp / t ck )? t ck 2)3)4)5)6) dq and dm input hold time t dh 0.5 ? ns 2)3)4)5) dq and dm input pulse width (each input) t dipw 1.75 ? ns 2)3)4)5)6) dqs output access time from ck/ck t dqsck ?0.75 +0.75 ns 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? t ck 2)3)4)5) dqs-dq skew (dqs and a ssociated dq signals) t dqsq ?+0.5nsfbga 2)3)4)5) write command to 1 st dqs latching transition t dqss 0.75 1.25 t ck 2)3)4)5) dq and dm input setup time t ds 0.5 ? ns 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? t ck 2)3)4)5) dqs falling edge to ck se tup time (write cycle) t dss 0.2 ? t ck 2)3)4)5) clock half period t hp min. ( t cl , t ch )? ns 2)3)4)5) data-out high-impedance time from ck/ck t hz ? +0.75 ns 2)3)4)5)7) address and control input hold time t ih 0.9 ? ns fast slew rate 3)4)5)6)8) 1.0 ? ns slow slew rate 3)4)5)6)8) control and addr. input pulse width (each input) t ipw 2.2 ? ns 2)3)4)5)9) address and control input setup time t is 0.9 ? ns fast slew rate 3)4)5)6)8) 1.0 ? ns slow slew rate 3)4)5)6)8) data-out low-impedance time from ck/ck t lz ?0.75 +0.75 ns 2)3)4)5)7) mode register set command cycle time t mrd 2? t ck 2)3)4)5) dq/dqs output hold time from dqs t qh t hp ? t qhs ?ns 2)3)4)5) data hold skew factor t qhs ?0.75nsfbga 2)3)4)5)
internet data sheet rev. 1.42, 2007-01 22 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module active to read w/ap delay t rap t rcd ?ns 2)3)4)5) active to precharge command t ras 45 120e+3 ns 2)3)4)5) active to active/auto-refresh command period t rc 65 ? ns 2)3)4)5) active to read or write delay t rcd 20 ? ns 2)3)4)5) average periodic refresh interval t refi 7.8 ? s 2)3)4)5)10) auto-refresh to active/auto-refresh command period t rfc 75 ? ns 2)3)4)5) precharge command period t rp 20 ? ns 2)3)4)5) read preamble t rpre 0.9 1.1 t ck 2)3)4)5) read postamble t rpst 0.4 0.6 t ck 2)3)4)5) active bank a to active bank b command t rrd 15 ? ns 2)3)4)5) write preamble t wpre 0.25 ? t ck 2)3)4)5) write preamble setup time t wpres 0?ns 2)3)4)5)11) write postamble t wpst 0.4 ? t ck 2)3)4)5)12) write recovery time t wr 15 ? ns 2)3)4)5) internal write to read command delay t wtr 1? t ck 2)3)4)5) exit self-refresh to non-read command t xsnr 75 ? ns 2)3)4)5)13) exit self-refresh to read command t xsrd 200 ? t ck 2)3)4)5) 1) v ddq = 2.5 v 0.2 v, vdd = +2.5 v 0.2 v ; 0 c t a 70 c 2) input slew rate 1 v/ns 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input refe rence level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 6) for each of the terms, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. 7) t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 8) fast slew rate 1.0 v/ns , slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ns, measured between v ih(ac) and v il(ac) . 9) these parameters guarantee device timing, but th ey are not necessarily tested on each device. 10) a maximum of eight autorefresh commands can be posted to any given ddr sdram device. 11) the specific requirement is that dqs be valid (high, low, or some point on a vali d transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progres s on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in pr ogress, dqs could be high, low, or transiti oning from high to low at this time, depending on t dqss . 12) the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 13) in all circumstances, t xsnr can be satisfied using t xsnr = trfc,min + 1 t ck parameter symbol ?7 unit note/test condition 1) ddr266a min. max.
internet data sheet rev. 1.42, 2007-01 23 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 4 spd codes this chapter lists all hexadecimal byte values stored in the eeprom of the products described in this data sheet. spd stands for serial presence detect. all values with xx in the table are module specific bytes which are defined during production. list of spd code tables ? table 16 ?hys72d[64/128/256]xxxgbr?5?b? on page 23 ? table 17 ?hys72d[64/128/256]xxxgbr?6?b? on page 27 ? table 18 ?hys72d[128/256]xxxgbr?7?b? on page 31 ? table 19 ?hys72d[128/256]xxxhbr?5?b? on page 35 ? table 20 ?hys72d[128/256]xxxhbr?6?b? on page 39 ? table 21 ?hys72d[128/256]xxxhbr?7?b? on page 43 table 16 hys72d[64/128/256]xxxgbr?5?b product type hys72d64301gbr?5?b hys72d128300gbr?5?b hys72d128321gbr?5?b hys72d256220gbr?5?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) label code pc3200r? 30331 pc3200r? 30331 pc3200r? 30331 pc3200r? 30331 jedec spd revision rev. 1.0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex 0 programmed spd bytes in e 2 prom 80 80 80 80 1 total number of bytes in e 2 prom 08 08 08 08 2 memory type (ddr = 07h) 07 07 07 07 3 number of row addresses 0d 0d 0d 0d 4 number of column addresses 0b 0c 0b 0c 5 number of dimm ranks 01 01 02 02 6 data width (lsb) 48484848 7 data width (msb) 00 00 00 00 8 interface voltage levels 04 04 04 04 9 t ck @ cl max (byte 18) [ns] 50 50 50 50
internet data sheet rev. 1.42, 2007-01 24 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 10 t ac sdram @ cl max (byte 18) [ns] 50 50 50 50 11 error correction support 02 02 02 02 12 refresh rate 82 82 82 82 13 primary sdram width 08 04 08 04 14 error checking sdram width 08 04 08 04 15 t ccd [cycles] 01 01 01 01 16 burst length supported 0e 0e 0e 0e 17 number of banks on sdram device 04 04 04 04 18 cas latency 1c1c1c1c 19 cs latency 01 01 01 01 20 write latency 02 02 02 02 21 dimm attributes 26 26 26 26 22 component attributes c1 c1 c1 c1 23 t ck @ cl max -0.5 (byte 18) [ns] 60 60 60 60 24 t ac sdram @ cl max -0.5 [ns] 50 50 50 50 25 t ck @ cl max -1 (byte 18) [ns] 75 75 75 75 26 t ac sdram @ cl max -1 [ns] 50 50 50 50 27 t rpmin [ns] 3c 3c 3c 3c 28 t rrdmin [ns] 28 28 28 28 29 t rcdmin [ns] 3c 3c 3c 3c 30 t rasmin [ns] 28 28 28 28 31 module density per rank 80 01 80 01 32 t as, t cs [ns] 60 60 60 60 33 t ah, t ch [ns] 60 60 60 60 34 t ds [ns] 40 40 40 40 product type hys72d64301gbr?5?b hys72d128300gbr?5?b hys72d128321gbr?5?b hys72d256220gbr?5?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) label code pc3200r? 30331 pc3200r? 30331 pc3200r? 30331 pc3200r? 30331 jedec spd revision rev. 1.0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex
internet data sheet rev. 1.42, 2007-01 25 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 35 t dh [ns] 40 40 40 40 36 - 40 not used 00 00 00 00 41 t rcmin [ns] 37 37 37 37 42 t rfcmin [ns] 41 41 41 41 43 t ckmax [ns] 28 28 28 28 44 t dqsqmax [ns] 28 28 28 28 45 t qhsmax [ns] 50 50 50 50 46 not used 00 00 00 00 47 dimm pcb height 01 01 01 01 48 - 61 not used 00 00 00 00 62 spd revision 10 10 10 10 63 checksum of byte 0-62 67 e1 68 e2 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 part number, char 1 37 37 37 37 74 part number, char 2 32 32 32 32 75 part number, char 3 44 44 44 44 76 part number, char 4 36 31 31 32 product type hys72d64301gbr?5?b hys72d128300gbr?5?b hys72d128321gbr?5?b hys72d256220gbr?5?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) label code pc3200r? 30331 pc3200r? 30331 pc3200r? 30331 pc3200r? 30331 jedec spd revision rev. 1.0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex
internet data sheet rev. 1.42, 2007-01 26 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 77 part number, char 5 34 32 32 35 78 part number, char 6 33 38 38 36 79 part number, char 7 30 33 33 32 80 part number, char 8 31 30 32 32 81 part number, char 9 47 30 31 30 82 part number, char 10 42 47 47 47 83 part number, char 11 52 42 42 42 84 part number, char 12 35 52 52 52 85 part number, char 13 42 35 35 35 86 part number, char 14 20 42 42 42 87 part number, char 15 20 20 20 20 88 part number, char 16 20 20 20 20 89 part number, char 17 20 20 20 20 90 part number, char 18 20 20 20 20 91 module revision code 0x 1x 1x 1x 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 - 98 module serial number xx xx xx xx 99 - 127 not used 00 00 00 00 product type hys72d64301gbr?5?b hys72d128300gbr?5?b hys72d128321gbr?5?b hys72d256220gbr?5?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) label code pc3200r? 30331 pc3200r? 30331 pc3200r? 30331 pc3200r? 30331 jedec spd revision rev. 1.0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex
internet data sheet rev. 1.42, 2007-01 27 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module table 17 hys72d[64/128/256]xxxgbr?6?b product type hys72d64301gbr?6?b hys72d128300gbr?6?b hys72d128321gbr?6?b hys72d256320gbr?6?b hys72d256220gbr?6?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 2 gbyte 72 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) 2 ranks ( 4) label code pc2700r ?25331 pc2700r ?25330 pc2700r ?25330 pc2700r ?25330 pc2700r ?25331 jedec spd revision rev. 1.0 rev . 0.0 rev. 0.0 rev. 0.0 rev. 1.0 byte# description hex hex hex hex hex 0 programmed spd bytes in e 2 prom 80 80 80 80 80 1 total number of bytes in e 2 prom 08 08 08 08 08 2 memory type (ddr = 07h) 07 07 07 07 07 3 number of row addresses 0d0d0d0d0d 4 number of column addresses 0b 0c 0b 0c 0c 5 number of dimm ranks 0101020202 6 data width (lsb) 4848484848 7 data width (msb) 00 00 00 00 00 8 interface voltage levels 04 04 04 04 04 9 t ck @ cl max (byte 18) [ns] 60 60 60 60 60 10 t ac sdram @ cl max (byte 18) [ns] 70 70 70 70 70 11 error correction support 02 02 02 02 02 12 refresh rate 82 82 82 82 82 13 primary sdram width 0804080404 14 error checking sdram width 0804080404 15 t ccd [cycles] 01 01 01 01 01 16 burst length supported 0e 0e 0e 0e 0e 17 number of banks on sdram device 04 04 04 04 04 18 cas latency 0c0c0c0c0c 19 cs latency 0101010101 20 write latency 0202020202 21 dimm attributes 26 26 26 26 26
internet data sheet rev. 1.42, 2007-01 28 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 22 component attributes c1 c1 c1 c1 c1 23 t ck @ cl max -0.5 (byte 18) [ns] 75 75 75 75 75 24 t ac sdram @ cl max -0.5 [ns] 70 70 70 70 70 25 t ck @ cl max -1 (byte 18) [ns] 00 00 00 00 00 26 t ac sdram @ cl max -1 [ns] 00 00 00 00 00 27 t rpmin [ns] 48 48 48 48 48 28 t rrdmin [ns] 30 30 30 30 30 29 t rcdmin [ns] 48 48 48 48 48 30 t rasmin [ns] 2a 2a 2a 2a 2a 31 module density per rank 80 01 80 01 01 32 t as, t cs [ns] 75 75 75 75 75 33 t ah, t ch [ns] 75 75 75 75 75 34 t ds [ns] 45 45 45 45 45 35 t dh [ns] 45 45 45 45 45 36 - 40 not used 00 00 00 00 00 41 t rcmin [ns] 3c 3c 3c 3c 3c 42 t rfcmin [ns] 48 48 48 48 48 43 t ckmax [ns] 30 30 30 30 30 44 t dqsqmax [ns] 28 28 28 28 28 45 t qhsmax [ns] 50 50 50 50 50 46 not used 00 00 00 00 00 47 dimm pcb height 01 00 00 00 01 48 - 61 not used 00 00 00 00 00 62 spd revision 10 00 00 00 10 63 checksum of byte 0-62 61 ca 51 cb dc product type hys72d64301gbr?6?b hys72d128300gbr?6?b hys72d128321gbr?6?b hys72d256320gbr?6?b hys72d256220gbr?6?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 2 gbyte 72 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) 2 ranks ( 4) label code pc2700r ?25331 pc2700r ?25330 pc2700r ?25330 pc2700r ?25330 pc2700r ?25331 jedec spd revision rev. 1.0 rev . 0.0 rev. 0.0 rev. 0.0 rev. 1.0 byte# description hex hex hex hex hex
internet data sheet rev. 1.42, 2007-01 29 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 00 72 module manufacturer location xx xx xx xx xx 73 part number, char 1 3737373737 74 part number, char 2 3232323232 75 part number, char 3 4444444444 76 part number, char 4 3631313232 77 part number, char 5 3432323535 78 part number, char 6 3338383636 79 part number, char 7 3033333332 80 part number, char 8 3130323232 81 part number, char 9 4730313030 82 part number, char 10 42 47 47 47 47 83 part number, char 11 52 42 42 42 42 84 part number, char 12 36 52 52 52 52 85 part number, char 13 42 36 36 36 36 86 part number, char 14 20 42 42 42 42 87 part number, char 15 20 20 20 20 20 88 part number, char 16 20 20 20 20 20 product type hys72d64301gbr?6?b hys72d128300gbr?6?b hys72d128321gbr?6?b hys72d256320gbr?6?b hys72d256220gbr?6?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 2 gbyte 72 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) 2 ranks ( 4) label code pc2700r ?25331 pc2700r ?25330 pc2700r ?25330 pc2700r ?25330 pc2700r ?25331 jedec spd revision rev. 1.0 rev . 0.0 rev. 0.0 rev. 0.0 rev. 1.0 byte# description hex hex hex hex hex
internet data sheet rev. 1.42, 2007-01 30 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 89 part number, char 17 20 20 20 20 20 90 part number, char 18 20 20 20 20 20 91 module revision code 0x 1x 1x 1x 1x 92 test program revision code xx xx xx xx xx 93 module manufacturing date year xx xx xx xx xx 94 module manufacturing date week xx xx xx xx xx 95 - 98 module serial number xx xx xx xx xx 99 - 127 not used 00 00 00 00 00 product type hys72d64301gbr?6?b hys72d128300gbr?6?b hys72d128321gbr?6?b hys72d256320gbr?6?b hys72d256220gbr?6?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 2 gbyte 72 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) 2 ranks ( 4) label code pc2700r ?25331 pc2700r ?25330 pc2700r ?25330 pc2700r ?25330 pc2700r ?25331 jedec spd revision rev. 1.0 rev . 0.0 rev. 0.0 rev. 0.0 rev. 1.0 byte# description hex hex hex hex hex
internet data sheet rev. 1.42, 2007-01 31 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module table 18 hys72d[128/256]xxxgbr?7?b product type hys72d128300gbr?7?b hys72d128321gbr?7?b hys72d256220gbr?7?b hys72d256320gbr?7?b organization 1 gbyte 1 gbyte 2 gbyte 2 gbyte 72 72 72 72 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) 2 ranks ( 4) label code pc2100r? 20330 pc2100r? 20330 pc2100r? 20331 pc2100r? 20330 jedec spd revision rev. 0.0 rev. 0.0 rev. 1.0 rev. 0.0 byte# description hex hex hex hex 0 programmed spd bytes in e 2 prom 80 80 80 80 1 total number of bytes in e 2 prom 08 08 08 08 2 memory type (ddr = 07h) 07 07 07 07 3 number of row addresses 0d 0d 0d 0d 4 number of column addresses 0c 0b 0c 0c 5 number of dimm ranks 01 02 02 02 6 data width (lsb) 48484848 7 data width (msb) 00 00 00 00 8 interface voltage levels 04 04 04 04 9 t ck @ cl max (byte 18) [ns] 70 70 70 70 10 t ac sdram @ cl max (byte 18) [ns] 75 75 75 75 11 error correction support 02 02 02 02 12 refresh rate 82 82 82 82 13 primary sdram width 04 08 04 04 14 error checking sdram width 04 08 04 04 15 t ccd [cycles] 01 01 01 01 16 burst length supported 0e 0e 0e 0e 17 number of banks on sdram device 04 04 04 04 18 cas latency 0c0c0c0c 19 cs latency 01 01 01 01 20 write latency 02 02 02 02 21 dimm attributes 26 26 26 26 22 component attributes c1 c1 c1 c1
internet data sheet rev. 1.42, 2007-01 32 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 23 t ck @ cl max -0.5 (byte 18) [ns] 75 75 75 75 24 t ac sdram @ cl max -0.5 [ns] 75 75 75 75 25 t ck @ cl max -1 (byte 18) [ns] 00 00 00 00 26 t ac sdram @ cl max -1 [ns] 00 00 00 00 27 t rpmin [ns] 50 50 50 50 28 t rrdmin [ns] 3c 3c 3c 3c 29 t rcdmin [ns] 50 50 50 50 30 t rasmin [ns] 2d 2d 2d 2d 31 module density per rank 01 80 01 01 32 t as, t cs [ns] 90 90 90 90 33 t ah, t ch [ns] 90 90 90 90 34 t ds [ns] 50 50 50 50 35 t dh [ns] 50 50 50 50 36 - 40 not used 00 00 00 00 41 t rcmin [ns] 41 41 41 41 42 t rfcmin [ns] 4b 4b 4b 4b 43 t ckmax [ns] 30 30 30 30 44 t dqsqmax [ns] 32 32 32 32 45 t qhsmax [ns] 75 75 75 75 46 not used 00 00 00 00 47 dimm pcb height 00 00 01 00 48 - 61 not used 00 00 00 00 62 spd revision 00 00 10 00 63 checksum of byte 0-62 86 0d 98 87 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f product type hys72d128300gbr?7?b hys72d128321gbr?7?b hys72d256220gbr?7?b hys72d256320gbr?7?b organization 1 gbyte 1 gbyte 2 gbyte 2 gbyte 72 72 72 72 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) 2 ranks ( 4) label code pc2100r? 20330 pc2100r? 20330 pc2100r? 20331 pc2100r? 20330 jedec spd revision rev. 0.0 rev. 0.0 rev. 1.0 rev. 0.0 byte# description hex hex hex hex
internet data sheet rev. 1.42, 2007-01 33 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 part number, char 1 37 37 37 37 74 part number, char 2 32 32 32 32 75 part number, char 3 44 44 44 44 76 part number, char 4 31 31 32 32 77 part number, char 5 32 32 35 35 78 part number, char 6 38 38 36 36 79 part number, char 7 33 33 32 33 80 part number, char 8 30 32 32 32 81 part number, char 9 30 31 30 30 82 part number, char 10 47 47 47 47 83 part number, char 11 42 42 42 42 84 part number, char 12 52 52 52 52 85 part number, char 13 37 37 37 37 86 part number, char 14 42 42 42 42 87 part number, char 15 20 20 20 20 88 part number, char 16 20 20 20 20 89 part number, char 17 20 20 20 20 product type hys72d128300gbr?7?b hys72d128321gbr?7?b hys72d256220gbr?7?b hys72d256320gbr?7?b organization 1 gbyte 1 gbyte 2 gbyte 2 gbyte 72 72 72 72 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) 2 ranks ( 4) label code pc2100r? 20330 pc2100r? 20330 pc2100r? 20331 pc2100r? 20330 jedec spd revision rev. 0.0 rev. 0.0 rev. 1.0 rev. 0.0 byte# description hex hex hex hex
internet data sheet rev. 1.42, 2007-01 34 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 90 part number, char 18 20 20 20 20 91 module revision code 1x 1x 1x 1x 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 - 98 module serial number xx xx xx xx 99 - 127 not used 00 00 00 00 product type hys72d128300gbr?7?b hys72d128321gbr?7?b hys72d256220gbr?7?b hys72d256320gbr?7?b organization 1 gbyte 1 gbyte 2 gbyte 2 gbyte 72 72 72 72 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) 2 ranks ( 4) label code pc2100r? 20330 pc2100r? 20330 pc2100r? 20331 pc2100r? 20330 jedec spd revision rev. 0.0 rev. 0.0 rev. 1.0 rev. 0.0 byte# description hex hex hex hex
internet data sheet rev. 1.42, 2007-01 35 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module table 19 hys72d[128/256]xxxhbr?5?b product type hys72d64301hbr?5?b hys72d128300hbr?5?b hys72d128321hbr?5?b hys72d256220hbr?5?b hys72d256320hbr?5?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 2 gbyte 72 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) 2 ranks ( 4) label code pc3200r ?30331 pc3200r ?30331 pc3200r ?30331 pc3200r ?30331 pc3200r ?30331 jedec spd revision rev. 1.0 rev . 1.0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex hex 0 programmed spd bytes in e 2 prom 80 80 80 80 80 1 total number of bytes in e 2 prom 08 08 08 08 08 2 memory type (ddr = 07h) 07 07 07 07 07 3 number of row addresses 0d0d0d0d0d 4 number of column addresses 0b 0c 0b 0c 0c 5 number of dimm ranks 0101020202 6 data width (lsb) 4848484848 7 data width (msb) 00 00 00 00 00 8 interface voltage levels 04 04 04 04 04 9 t ck @ cl max (byte 18) [ns] 50 50 50 50 50 10 t ac sdram @ cl max (byte 18) [ns] 50 50 50 50 50 11 error correction support 02 02 02 02 02 12 refresh rate 82 82 82 82 82 13 primary sdram width 0804080404 14 error checking sdram width 0804080404 15 t ccd [cycles] 01 01 01 01 01 16 burst length supported 0e 0e 0e 0e 0e 17 number of banks on sdram device 04 04 04 04 04 18 cas latency 1c1c1c1c1c 19 cs latency 0101010101 20 write latency 0202020202 21 dimm attributes 26 26 26 26 26
internet data sheet rev. 1.42, 2007-01 36 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 22 component attributes c1 c1 c1 c1 c1 23 t ck @ cl max -0.5 (byte 18) [ns] 60 60 60 60 60 24 t ac sdram @ cl max -0.5 [ns] 50 50 50 50 50 25 t ck @ cl max -1 (byte 18) [ns] 75 75 75 75 75 26 t ac sdram @ cl max -1 [ns] 50 50 50 50 50 27 t rpmin [ns] 3c 3c 3c 3c 3c 28 t rrdmin [ns] 28 28 28 28 28 29 t rcdmin [ns] 3c 3c 3c 3c 3c 30 t rasmin [ns] 28 28 28 28 28 31 module density per rank 80 01 80 01 01 32 t as, t cs [ns] 60 60 60 60 60 33 t ah, t ch [ns] 60 60 60 60 60 34 t ds [ns] 40 40 40 40 40 35 t dh [ns] 40 40 40 40 40 36 - 40 not used 00 00 00 00 00 41 t rcmin [ns] 37 37 37 37 37 42 t rfcmin [ns] 41 41 41 41 41 43 t ckmax [ns] 28 28 28 28 28 44 t dqsqmax [ns] 28 28 28 28 28 45 t qhsmax [ns] 50 50 50 50 50 46 not used 00 00 00 00 00 47 dimm pcb height 01 01 01 01 01 48 - 61 not used 00 00 00 00 00 62 spd revision 10 10 10 10 10 63 checksum of byte 0-62 67 e1 68 e2 e2 product type hys72d64301hbr?5?b hys72d128300hbr?5?b hys72d128321hbr?5?b hys72d256220hbr?5?b hys72d256320hbr?5?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 2 gbyte 72 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) 2 ranks ( 4) label code pc3200r ?30331 pc3200r ?30331 pc3200r ?30331 pc3200r ?30331 pc3200r ?30331 jedec spd revision rev. 1.0 rev . 1.0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex hex
internet data sheet rev. 1.42, 2007-01 37 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 00 72 module manufacturer location xx xx xx xx xx 73 part number, char 1 3737373737 74 part number, char 2 3232323232 75 part number, char 3 4444444444 76 part number, char 4 3631313232 77 part number, char 5 3432323535 78 part number, char 6 3338383636 79 part number, char 7 3033333233 80 part number, char 8 3130323232 81 part number, char 9 4830313030 82 part number, char 10 42 48 48 48 48 83 part number, char 11 52 42 42 42 42 84 part number, char 12 35 52 52 52 52 85 part number, char 13 42 35 35 35 35 86 part number, char 14 20 42 42 42 42 87 part number, char 15 20 20 20 20 20 88 part number, char 16 20 20 20 20 20 product type hys72d64301hbr?5?b hys72d128300hbr?5?b hys72d128321hbr?5?b hys72d256220hbr?5?b hys72d256320hbr?5?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 2 gbyte 72 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) 2 ranks ( 4) label code pc3200r ?30331 pc3200r ?30331 pc3200r ?30331 pc3200r ?30331 pc3200r ?30331 jedec spd revision rev. 1.0 rev . 1.0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex hex
internet data sheet rev. 1.42, 2007-01 38 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 89 part number, char 17 20 20 20 20 20 90 part number, char 18 20 20 20 20 20 91 module revision code 1x 1x 1x 1x 1x 92 test program revision code xx xx xx xx xx 93 module manufacturing date year xx xx xx xx xx 94 module manufacturing date week xx xx xx xx xx 95 - 98 module serial number xx xx xx xx xx 99 - 127 not used 00 00 00 00 00 product type hys72d64301hbr?5?b hys72d128300hbr?5?b hys72d128321hbr?5?b hys72d256220hbr?5?b hys72d256320hbr?5?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 2 gbyte 72 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) 2 ranks ( 4) label code pc3200r ?30331 pc3200r ?30331 pc3200r ?30331 pc3200r ?30331 pc3200r ?30331 jedec spd revision rev. 1.0 rev . 1.0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex hex
internet data sheet rev. 1.42, 2007-01 39 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module table 20 hys72d[128/256]xxxhbr?6?b product type hys72d64301hbr?6?b hys72d128300hbr?6?b hys72d128321hbr?6?b hys72d256220hbr?6?b hys72d256320hbr?6?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 2 gbyte 72 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) 2 ranks ( 4) label code pc2700r ?25331 pc2700r ?25330 pc2700r ?25330 pc2700r ?25331 pc2700r ?25330 jedec spd revision rev. 1.0 rev . 0.0 rev. 0.0 rev. 1.0 rev. 0.0 byte# description hex hex hex hex hex 0 programmed spd bytes in e 2 prom 80 80 80 80 80 1 total number of bytes in e 2 prom 08 08 08 08 08 2 memory type (ddr = 07h) 07 07 07 07 07 3 number of row addresses 0d0d0d0d0d 4 number of column addresses 0b 0c 0b 0c 0c 5 number of dimm ranks 0101020202 6 data width (lsb) 4848484848 7 data width (msb) 00 00 00 00 00 8 interface voltage levels 04 04 04 04 04 9 t ck @ cl max (byte 18) [ns] 60 60 60 60 60 10 t ac sdram @ cl max (byte 18) [ns] 70 70 70 70 70 11 error correction support 02 02 02 02 02 12 refresh rate 82 82 82 82 82 13 primary sdram width 0804080404 14 error checking sdram width 0804080404 15 t ccd [cycles] 01 01 01 01 01 16 burst length supported 0e 0e 0e 0e 0e 17 number of banks on sdram device 04 04 04 04 04 18 cas latency 0c0c0c0c0c 19 cs latency 0101010101 20 write latency 0202020202 21 dimm attributes 26 26 26 26 26
internet data sheet rev. 1.42, 2007-01 40 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 22 component attributes c1 c1 c1 c1 c1 23 t ck @ cl max -0.5 (byte 18) [ns] 75 75 75 75 75 24 t ac sdram @ cl max -0.5 [ns] 70 70 70 70 70 25 t ck @ cl max -1 (byte 18) [ns] 00 00 00 00 00 26 t ac sdram @ cl max -1 [ns] 00 00 00 00 00 27 t rpmin [ns] 48 48 48 48 48 28 t rrdmin [ns] 30 30 30 30 30 29 t rcdmin [ns] 48 48 48 48 48 30 t rasmin [ns] 2a 2a 2a 2a 2a 31 module density per rank 80 01 80 01 01 32 t as, t cs [ns] 75 75 75 75 75 33 t ah, t ch [ns] 75 75 75 75 75 34 t ds [ns] 45 45 45 45 45 35 t dh [ns] 45 45 45 45 45 36 - 40 not used 00 00 00 00 00 41 t rcmin [ns] 3c 3c 3c 3c 3c 42 t rfcmin [ns] 48 48 48 48 48 43 t ckmax [ns] 30 30 30 30 30 44 t dqsqmax [ns] 28 28 28 28 28 45 t qhsmax [ns] 50 50 50 50 50 46 not used 00 00 00 00 00 47 dimm pcb height 01 00 00 01 00 48 - 61 not used 00 00 00 00 00 62 spd revision 10 00 00 10 00 63 checksum of byte 0-62 61 ca 51 dc cb product type hys72d64301hbr?6?b hys72d128300hbr?6?b hys72d128321hbr?6?b hys72d256220hbr?6?b hys72d256320hbr?6?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 2 gbyte 72 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) 2 ranks ( 4) label code pc2700r ?25331 pc2700r ?25330 pc2700r ?25330 pc2700r ?25331 pc2700r ?25330 jedec spd revision rev. 1.0 rev . 0.0 rev. 0.0 rev. 1.0 rev. 0.0 byte# description hex hex hex hex hex
internet data sheet rev. 1.42, 2007-01 41 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 00 72 module manufacturer location xx xx xx xx xx 73 part number, char 1 3737373737 74 part number, char 2 3232323232 75 part number, char 3 4444444444 76 part number, char 4 3631313232 77 part number, char 5 3432323535 78 part number, char 6 3338383636 79 part number, char 7 3033333233 80 part number, char 8 3130323232 81 part number, char 9 4830313030 82 part number, char 10 42 48 48 48 48 83 part number, char 11 52 42 42 42 42 84 part number, char 12 36 52 52 52 52 85 part number, char 13 42 36 36 36 36 86 part number, char 14 20 42 42 42 42 87 part number, char 15 20 20 20 20 20 88 part number, char 16 20 20 20 20 20 product type hys72d64301hbr?6?b hys72d128300hbr?6?b hys72d128321hbr?6?b hys72d256220hbr?6?b hys72d256320hbr?6?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 2 gbyte 72 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) 2 ranks ( 4) label code pc2700r ?25331 pc2700r ?25330 pc2700r ?25330 pc2700r ?25331 pc2700r ?25330 jedec spd revision rev. 1.0 rev . 0.0 rev. 0.0 rev. 1.0 rev. 0.0 byte# description hex hex hex hex hex
internet data sheet rev. 1.42, 2007-01 42 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 89 part number, char 17 20 20 20 20 20 90 part number, char 18 20 20 20 20 20 91 module revision code 1x 1x 1x 1x 1x 92 test program revision code xx xx xx xx xx 93 module manufacturing date year xx xx xx xx xx 94 module manufacturing date week xx xx xx xx xx 95 - 98 module serial number xx xx xx xx xx 99 - 127 not used 00 00 00 00 00 product type hys72d64301hbr?6?b hys72d128300hbr?6?b hys72d128321hbr?6?b hys72d256220hbr?6?b hys72d256320hbr?6?b organization 512mb 1 gbyte 1 gbyte 2 gbyte 2 gbyte 72 72 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) 2 ranks ( 4) label code pc2700r ?25331 pc2700r ?25330 pc2700r ?25330 pc2700r ?25331 pc2700r ?25330 jedec spd revision rev. 1.0 rev . 0.0 rev. 0.0 rev. 1.0 rev. 0.0 byte# description hex hex hex hex hex
internet data sheet rev. 1.42, 2007-01 43 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module table 21 hys72d[128/256]xxxhbr?7?b product type hys72d128300hbr?7?b hys72d128321hbr?7?b hys72d256220hbr?7?b hys72d256320hbr?7?b organization 1 gbyte 1 gbyte 2 gbyte 2 gbyte 72 72 72 72 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) 2 ranks ( 4) label code pc2100r? 20330 pc2100r? 20330 pc2100r? 20331 pc2100r? 20330 jedec spd revision rev. 0.0 rev. 0.0 rev. 1.0 rev. 0.0 byte# description hex hex hex hex 0 programmed spd bytes in e 2 prom 80 80 80 80 1 total number of bytes in e 2 prom 08 08 08 08 2 memory type (ddr = 07h) 07 07 07 07 3 number of row addresses 0d 0d 0d 0d 4 number of column addresses 0c 0b 0c 0c 5 number of dimm ranks 01 02 02 02 6 data width (lsb) 48484848 7 data width (msb) 00 00 00 00 8 interface voltage levels 04 04 04 04 9 t ck @ cl max (byte 18) [ns] 70 70 70 70 10 t ac sdram @ cl max (byte 18) [ns] 75 75 75 75 11 error correction support 02 02 02 02 12 refresh rate 82 82 82 82 13 primary sdram width 04 08 04 04 14 error checking sdram width 04 08 04 04 15 t ccd [cycles] 01 01 01 01 16 burst length supported 0e 0e 0e 0e 17 number of banks on sdram device 04 04 04 04 18 cas latency 0c0c0c0c 19 cs latency 01 01 01 01 20 write latency 02 02 02 02 21 dimm attributes 26 26 26 26 22 component attributes c1 c1 c1 c1
internet data sheet rev. 1.42, 2007-01 44 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 23 t ck @ cl max -0.5 (byte 18) [ns] 75 75 75 75 24 t ac sdram @ cl max -0.5 [ns] 75 75 75 75 25 t ck @ cl max -1 (byte 18) [ns] 00 00 00 00 26 t ac sdram @ cl max -1 [ns] 00 00 00 00 27 t rpmin [ns] 50 50 50 50 28 t rrdmin [ns] 3c 3c 3c 3c 29 t rcdmin [ns] 50 50 50 50 30 t rasmin [ns] 2d 2d 2d 2d 31 module density per rank 01 80 01 01 32 t as, t cs [ns] 90 90 90 90 33 t ah, t ch [ns] 90 90 90 90 34 t ds [ns] 50 50 50 50 35 t dh [ns] 50 50 50 50 36 - 40 not used 00 00 00 00 41 t rcmin [ns] 41 41 41 41 42 t rfcmin [ns] 4b 4b 4b 4b 43 t ckmax [ns] 30 30 30 30 44 t dqsqmax [ns] 32 32 32 32 45 t qhsmax [ns] 75 75 75 75 46 not used 00 00 00 00 47 dimm pcb height 00 00 01 00 48 - 61 not used 00 00 00 00 62 spd revision 00 00 10 00 63 checksum of byte 0-62 86 0d 98 87 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f product type hys72d128300hbr?7?b hys72d128321hbr?7?b hys72d256220hbr?7?b hys72d256320hbr?7?b organization 1 gbyte 1 gbyte 2 gbyte 2 gbyte 72 72 72 72 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) 2 ranks ( 4) label code pc2100r? 20330 pc2100r? 20330 pc2100r? 20331 pc2100r? 20330 jedec spd revision rev. 0.0 rev. 0.0 rev. 1.0 rev. 0.0 byte# description hex hex hex hex
internet data sheet rev. 1.42, 2007-01 45 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 part number, char 1 37 37 37 37 74 part number, char 2 32 32 32 32 75 part number, char 3 44 44 44 44 76 part number, char 4 31 31 32 32 77 part number, char 5 32 32 35 35 78 part number, char 6 38 38 36 36 79 part number, char 7 33 33 32 33 80 part number, char 8 30 32 32 32 81 part number, char 9 30 31 30 30 82 part number, char 10 48 48 48 48 83 part number, char 11 42 42 42 42 84 part number, char 12 52 52 52 52 85 part number, char 13 37 37 37 37 86 part number, char 14 42 42 42 42 87 part number, char 15 20 20 20 20 88 part number, char 16 20 20 20 20 89 part number, char 17 20 20 20 20 90 part number, char 18 20 20 20 20 91 module revision code 1x 1x 1x 1x product type hys72d128300hbr?7?b hys72d128321hbr?7?b hys72d256220hbr?7?b hys72d256320hbr?7?b organization 1 gbyte 1 gbyte 2 gbyte 2 gbyte 72 72 72 72 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) 2 ranks ( 4) label code pc2100r? 20330 pc2100r? 20330 pc2100r? 20331 pc2100r? 20330 jedec spd revision rev. 0.0 rev. 0.0 rev. 1.0 rev. 0.0 byte# description hex hex hex hex
internet data sheet rev. 1.42, 2007-01 46 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 - 98 module serial number xx xx xx xx 99 - 127 not used 00 00 00 00 product type hys72d128300hbr?7?b hys72d128321hbr?7?b hys72d256220hbr?7?b hys72d256320hbr?7?b organization 1 gbyte 1 gbyte 2 gbyte 2 gbyte 72 72 72 72 1 rank ( 4) 2 ranks ( 8) 2 ranks ( 4) 2 ranks ( 4) label code pc2100r? 20330 pc2100r? 20330 pc2100r? 20331 pc2100r? 20330 jedec spd revision rev. 0.0 rev. 0.0 rev. 1.0 rev. 0.0 byte# description hex hex hex hex
internet data sheet rev. 1.42, 2007-01 47 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 5 package outline figure 2 package outline raw card c - l-dim-184-22-2 notes 1. drawing according to iso 8015 2. dimensions in mm 3. general tolerances +/- 0.15 128.95 2.5 1 64.77 ?0.1 0.1 a bc 4 0.1 0.1 a 120.65 6.35 1.27 95 x = 2.175 49.53 a c b 133.35 92 b 0.13 28.58 0.15 b a c 0.13 0.05 1 1.27 0.1 ab c detail of contacts 0.2 2.5 0.2 3.8 93 1.8 0.1 c 0.1 ab 17.8 184 10 1.27 0.4 c 0.1 4 max. burr max. 0.4 allowed 3 min. 6.62
internet data sheet rev. 1.42, 2007-01 48 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module figure 3 package outline raw card b - l-dim-184-23-2 notes 1. drawing according to iso 8015 2. dimensions in mm 3. general tolerances +/- 0.15 4 max. 1.27 c 0.1 0.4 0.1 ?0.1 0.1 2.5 0.1 4 1 x 95 c 64.77 ab 120.65 1.27 = 2.175 6.35 a b c a 133.35 128.95 49.53 92 0.15 c ab 0.13 b 28.58 b a 0.1 c 1.8 c 1 b 0.1 a detail of contacts 0.2 1.27 3.8 0.13 93 0.2 2.5 0.05 17.8 184 10 0.1 3 min. burr max. 0.4 allowed 6.62
internet data sheet rev. 1.42, 2007-01 49 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module figure 4 package outline raw card f ? l-dim-184-25 notes 1. drawing according to iso 8015 2. dimensions in mm 3. general tolerances +/- 0.15 128.95 133.35 0.15 a bc a a 6.62 6.35 2.175 49.53 92 0.1 2.5 ?0.1 c ab 1 64.77 0.13 30.48 b 0.1 4 0.1 b a c 4 max. c 0.4 0.1 1.27 1.8 0.1 0.1 b ac 0.13 3.8 3 min. 17.8 10 93 184 burr max. 0.4 allowed detail of contacts 0.2 1.27 0.05 1 0.1 ab c 0.2 2.5 l-dim-184-25
internet data sheet rev. 1.42, 2007-01 50 03292006-7cza-ys85 hys72d[64/128/256]xx x[g/h]br?[5/6/7]?b registered ddr sdram module 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 spd codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table of contents
edition 2007-01 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2007. all rights reserved. legal disclaimer the information given in this internet data sheet shall in no ev ent be regarded as a guarantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hi nts given herein, any typical values stated herein and/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any kin d, including without limitation warranties of non-infringem ent of intellectual property rights of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com internet data sheet

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